The present invention generally relates to delay lock loop (DLL) devices and clock recovery, and more particularly, to a system and method for using control logic and phase inversion to generate an eight phase selector from a four to one selector.
Delay locked loops (DLL) and phase locked loops (PLL) are commonly used to align a particular signal with the same frequency and phase of a reference clock signal. PLL and DLL may be used for various applications such as generating a clean periodic signal from a noisy signal, frequency multiplication, and clock and data recovery. A PLL is an electronic circuit that controls an oscillator, so that the oscillator maintains a constant phase angle relative to a reference signal. Clock recovery circuits typically use a PLL circuit to minimize the phase offset between the clock and data.
The main difference between a PLL and a DLL is that a PLL uses a voltage controlled oscillator (VCO) whose frequency is controlled by the loop, while a DLL uses a variable delay or phase shifter whose delay is controlled by the loop. A VCO is an element where a control voltage varies the output frequency and phase, such that the output is a periodic signal at a desired frequency. The PLL allows the VCO output to be phase locked to an external reference signal. The phase of the VCO output and the reference signal are compared by a phase detector, which generates an output signal indicating whether the VCO output signal is early or late compared to the reference signal. The phase detector output is filtered by a loop filter (e.g., an integrator), which generates a control voltage that controls the frequency of the VCO. As such, the VCO output frequency and phase are adjusted to match the reference frequency and phase.
The basic elements of a DLL include a phase detector, a phase selector, a loop filter, and a variable delay. A DLL is similar to a PLL, but uses a variable delay or phase shifter element instead of a VCO. However, since the delay does not generate a periodic signal directly, an external source to the DLL is usually required. A periodic signal is input to the DLL and delayed by a variable delay or phase shifter to generate a delayed version of the input signal. A reference input is provided at an input port of the phase detector. The DLL output can be phase locked to the reference input, if the periodic input signal is relatively close in frequency to the reference input. The variable delay can be varied in such a way as to ensure that the phase of the output of the DLL substantially tracks the phase of the reference input. The DLL provides the phase tracking mechanism by using a phase detector that compares the relative phase of the DLL output and the reference input to generate a phase detector output that is proportional to the difference in phase. The phase difference is then integrated by an integrator coupled to the phase detector. The integrator generates a control voltage to adjust the delay in the variable delay, essentially trying to zero out the difference in phase between the DLL output and the reference input.
The phase selector of a DLL is discrete, where the phase shift occurs in discrete rather than continuous increments, as in a PLL. One advantage of a discrete phase selector over a continuous phase selector is the ease with which multiple periods of delay can be implemented. This gives the discrete phase selector almost infinite range. A discrete phase selector is typically implemented as a multiplexor, where each input consists of a phase shifted version of the reference clock. However, traditional multiplexors are inadequate for use in high frequency clock recovery due to the high power and limited bandwidth (i.e., where a large number of inputs are required). There is the possibility of glitches or phase discontinuities in the output of traditional multiplexors when the selector control is changed. A system and method for improving clock recovery by simplifying the use of traditional multiplexors in DLLs is desirable.
The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary embodiment of the present invention includes a high speed phase selector system having control logic using Gray coding to generate at least one control signal. For example, the control logic uses a 3 bit word to select a phase for clock recovery. By using a slightly delayed version of a control signal and selecting adjacent phases for transitioning, smooth phase transitions may be had at the outputs of the high speed phase selector. A selector coupled to the control logic determines the phase selected. XOR gates coupled between the control logic and the selector provide eight phases of a clock using four input phases of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates.